Response status management in a social networking environment

ABSTRACT

An embodiment of the invention may include a semiconductor structure for ensuring semiconductor design integrity. The semiconductor structure may include an electrical circuit necessary for the operation of the semiconductor circuit and white space having no electrical circuit. The semiconductor structure may include an optical pattern used for validating the semiconductor circuit design formed in the white space of the electrical circuit. In an embodiment of the invention, the optical pattern may include one or more deposition layers. In an embodiment of the invention, the optical pattern may include covershapes. In an embodiment of the invention, the optical pattern may be physically isolated from the electrical circuit. The optical pattern may include a Moiré pattern.

BACKGROUND

The present invention generally relates to semiconductor maskmanufacture, and particularly to optical validation of semiconductormasks.

Semiconductor photomasks are designed to define circuit patterns for thetransitions and interconnect layers. The photomask design also containswhite space in between and around the circuit patterns for thetransitions and interconnect layers. The greater the available whitespace on a photomask, the greater the possibility of additional circuitelements being added to the design by a third party.

BRIEF SUMMARY

An embodiment of the invention may include a semiconductor structure.The semiconductor structure may include an electrical circuit necessaryfor the operation of the semiconductor circuit. The semiconductorstructure may include white space, which may have no electrical circuit.The semiconductor structure may include an optical pattern formed in thewhite space of the electrical circuit for validating the semiconductorcircuit design. In an embodiment of the invention, the optical patternmay include one or more deposition layers. In an embodiment of theinvention, the optical pattern may include covershapes. In an embodimentof the invention, the optical pattern may be physically isolated fromthe electrical circuit. The optical pattern may include a Moiré pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description, given by way of example and notintended to limit the invention solely thereto, will best be appreciatedin conjunction with the accompanying drawings, in which:

FIG. 1 is a flow chart of a method for optically validating the correctmask was used during semiconductor manufacture, according to anembodiment of the present invention;

FIG. 2a is a plan view of a photomask for a semiconductor, according toan embodiment of the present invention;

FIG. 2b illustrates an example optical fingerprint design, according toan embodiment of the present invention;

FIG. 2c illustrates an example optical fingerprint design, according toan embodiment of the present invention;

FIG. 2d is plan view of a semiconductor design for a first depositionlayer with an optical fingerprint, according to an embodiment of thepresent invention;

FIG. 2e is plan view of a semiconductor design for a second depositionlayer with an optical fingerprint, according to an embodiment of thepresent invention; and

FIG. 2f is plan view of a semiconductor design for a first and seconddeposition layer with an optical fingerprint, according to an embodimentof the present invention.

Elements of the figures are not necessarily to scale and are notintended to portray specific parameters of the invention. For clarityand ease of illustration, scale of elements may be exaggerated. Thedetailed description should be consulted for accurate dimensions. Thedrawings are intended to depict only typical embodiments of theinvention, and therefore should not be considered as limiting the scopeof the invention. In the drawings, like numbering represents likeelements.

DETAILED DESCRIPTION

The following description with reference to the accompanying drawings isprovided to assist in a comprehensive understanding of exemplaryembodiments of the invention as defined by the claims and theirequivalents. It includes various specific details to assist in thatunderstanding but these are to be regarded as merely exemplary.Accordingly, those of ordinary skill in the art will recognize thatvarious changes and modifications of the embodiments described hereincan be made without departing from the scope and spirit of theinvention. In addition, descriptions of well-known functions andconstructions may be omitted for clarity and conciseness.

The terms and words used in the following description and claims are notlimited to the bibliographical meanings, but, are merely used to enablea clear and consistent understanding of the invention. Accordingly, itshould be apparent to those skilled in the art that the followingdescription of exemplary embodiments of the present invention isprovided for illustration purpose only and not for the purpose oflimiting the invention as defined by the appended claims and theirequivalents.

It is to be understood that the singular forms “a,” “an,” and “the”include plural referents unless the context clearly dictates otherwise.Thus, for example, reference to “a component surface” includes referenceto one or more of such surfaces unless the context clearly dictatesotherwise.

In the interest of not obscuring the presentation of embodiments of thepresent invention, in the following detailed description, someprocessing steps or operations that are known in the art may have beencombined together for presentation and for illustration purposes and insome instances may have not been described in detail. In otherinstances, some processing steps or operations that are known in the artmay not be described at all. It should be understood that the followingdescription is rather focused on the distinctive features or elements ofvarious embodiments of the present invention.

Embodiments of the invention generally relate to methods of opticallyvalidating the usage of a photomask in semiconductor manufacture.Semiconductor photomasks define the circuit patterns for the transitionsand interconnect layers. Photomasks also contain white space in betweenand around the circuit patterns for the transitions and interconnectlayers which allow for the possibility of unwanted additional circuitelements being added by a third party. The present invention uses analgorithm to analyze the available white space on a photomask anddesigns an optical pattern to be inserted on the photomask to consumethe white space. The optical pattern may be viewed under a microscopeand/or using a light source. Thus, the present invention prevents theaddition of unwanted circuit elements into the design for asemiconductor by providing an optically viewable pattern to occupy thewhite space in a photomask design.

Embodiments of the present invention will now be described in detailwith reference to the accompanying Figures.

FIG. 1 is a flow chart of a method for optically validating the correctmask was used during semiconductor manufacture, according to anembodiment of the present invention. Referring to FIG. 1, the method 100includes a step 110, designing a photomask; a step 112, running afingerprint algorithm; a step 114, inserting an optical fingerprint inthe white space of the photomask; a step 116, enhancing the photomaskusing optical proximity correction; a step 118, building a mask; a step120, building a wafer; a step 122, testing the optical patterns of thewafer; a step 124, comparing the optical patterns of the wafer to knownoptical patterns of the optical fingerprint design; a step 126,validating the wafer when the optical patterns match; and a step 128,discarding the wafer when the optical patterns do not match. Steps ofthe method 100 embodied in FIG. 1 are depicted in FIGS. 2a -f.

Referring to step S110, described in conjunction with FIG. 2a , aphotomask 210 is designed, photomask 210, defining a design fordeposition layer 212 for interconnect layers in a semiconductor chip214. Photomask 210 design may contain white space 216, i.e. areas of nodesign, in between and around the circuit designs for the transitionsand interconnect layers for semiconductor each chip 214. Photomask 210may also contain a kerf 218, i.e., white space in between the one ormore semiconductor chip 214 designs where the semiconductor chips 214 ofa single wafer are cut apart. It may be appreciated that eachsemiconductor chip 214 is designed using multiple different photomasks210, each photomask 210 defining circuit structures in a depositionlayer 212, which are layered on top of one another.

Referring to step S112, described in conjunction with FIGS. 2b-c , afingerprint algorithm is run to design an optical fingerprint 220 to fitwithin the available white space 216 of the design for semiconductorchips 214 on photomask 210. For example, the fingerprint algorithm mayanalyze the white space 216 of the design of objects to be printed, thesizes of the designed objects to be printed and the critical aspects ofthe designed objects to be printed for semiconductor chips 214 onphotomask 210 and calculate an optical design to fit within white space216. The fingerprint algorithm may analyze all photomasks 210 that willbe used to manufacture semiconductor chip 214 to create opticalfingerprint 220. The fingerprint algorithm may account for the overlayand placement of the generated fill structures of the design of opticalfingerprint 220 between layers of optical fingerprint 220 to ensure thatthey are able to be tested and/or visually assessed during andpost-manufacturing for validity against the inserted fill. For example,optical fingerprint 220 as illustrated in FIGS. 2b-c shows an opticalfingerprint design for multiple photomasks 210 layered on top of oneanother, i.e. designs for subsequent deposition layers 212. In anembodiment of the invention, the fingerprint algorithm may intentionallyomit certain overlay/contact points between layers in opticalfingerprint 220. For example, the fingerprint algorithm may use, but isnot limited to, a covershape approach to determine the regularity andplacement of intentionally omitted shapes within the circuit design ofoptical fingerprint 220. The covershape definitions may be restricted tothe fill definition and fingerprint algorithm and may not be shared withthe subsequent manufacturing steps, and thus remain protected which mayallow the unique covershape designs to be optically recognized.

Optical fingerprint 220 may be a design for trenches to be etched intothe deposition layer 212 of semiconductor chip 214. In anotherembodiment of the invention, the optical fingerprint 220 may also bedesigned to fit within kerf 218 on photomask 210 between the designs forsemiconductor chips 214.

Referring to step S114, described in conjunction with FIGS. 2d-f , theoptical fingerprint 220 is inserted in the white space 216 of thephotomask 210 design. FIG. 2d illustrates a first photomask 210 acorresponding to a first deposition layer of semiconductor chip 214 witha first optical fingerprint 220 a. FIG. 2e illustrates a secondphotomask 210 b corresponding to a second deposition layer ofsemiconductor chip 214 with a second optical fingerprint 220 b. FIG. 2fillustrates semiconductor chip 214 with the designs for first depositionlayer with optical fingerprint 220 a and second deposition layer withoptical fingerprint 220 b with overlap area 222. It can be appreciatedthat semiconductor chip 214 may consist of many deposition layers 212,with each deposition layer 212 having a unique design and opticalfingerprint 220. Further, it can be appreciated that semiconductor chip214 with deposition layers 212 with optical fingerprint 220 may havemultiple overlap areas 222 Overlap areas 222 may have unique patternthat can be viewed using a light source or a microscope such as, but notlimited to a Moiré pattern.

Referring to step S116, the photomask design containing thesemiconductor circuit design and the design for optical fingerprint 220may be optionally enhanced using optical proximity correction. Opticalproximity correction is a photolithography enhancement technique used tocompensate for image errors due to diffraction or process effects.

Referring to step S118, a photomask is built according to the photomaskdesign to include optical fingerprint 220, and a wafer is fabricatedusing the photomask at step S120. The trenches to be etched into thedeposition layer 212 of semiconductor chip 214 may contain metal and/orsilicon depending on deposition layer 212. For example, semiconductorfabrication consists of several stages including, Front-End-Of-The-Line(FEOL), Middle-Of-The-Line (MOL), and Back-End-Of-The-Line (BEOL)processes. For deposition layers 212 created in FEOL processes, thetrenches may be filled with a either silicon, such as, but not limitedto Poly Silicon, or Amorphous Silicon, or a metal, such as, but notlimited to, copper, aluminum, or tungsten. For deposition layers 212created in MOL or BEOL processes, the trenches may be filled with ametal, such as, but not limited to, copper, aluminum, or tungsten. In anembodiment of the invention, steps S110-S120 may be repeated until alldeposition layers 212 of semiconductor chip 214 are completed.

Referring to step S122, the wafer is optically analyzed to confirm thecorrect photomask design was used. For example, the trenches of thedifferent deposition layers 212 of optical fingerprint 220 design mayhave a unique overlap pattern. For example, overlap areas 222 x may formMoiré patterns. The wafer may be analyzed using a light source, such as,but not limited to, an ultraviolet (UV) light source to illuminatesemiconductor chip 214. In an embodiment of the invention, the wafer maybe analyzed using a microscope. The wafer may be optically analyzedafter each deposition layer 212 has been deposited. In an embodiment ofthe invention, the wafer may be analyzed after two or more depositionlayers 212 of semiconductor chip 214 have been deposited.

Referring to step S124, the optical patterns of the wafer are comparedto the known optical patterns of optical fingerprint 220. When theoptical patterns of the wafer match the known optical patterns ofoptical fingerprint 220, the wafer is validated at step S126. When theoptical patterns of the wafer do not match the known optical patterns ofoptical fingerprint 220, the wafer is discarded at step S128. In anembodiment of the invention, the wafer may be compared to knowncovershape designs.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiment, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein. It is therefore intended that the present inventionnot be limited to the exact forms and details described and illustratedbut fall within the scope of the appended claims.

What is claimed is:
 1. A semiconductor structure comprising: anelectrical circuit necessary for the operation of the semiconductorcircuit, and white space, wherein the white space has no electricalcircuit; and an optical pattern formed in the white space of theelectrical circuit, wherein the optical pattern is used for validatingthe semiconductor circuit design.
 2. The structure of claim 1, whereinthe optical pattern comprises one or more deposition layers.
 3. Thestructure of claim 1, wherein the optical pattern comprises covershapes.4. The structure of claim 1, wherein the optical pattern is physicallyisolated from the electrical circuit.
 5. The structure of claim 1,wherein the optical pattern comprises a Moiré pattern.